Hello everyone! I am a senior FAE engineer from Shanghai Leiditech. As a "lightning and ESD protection expert" in the electronics industry, our role is not to provide simple on/off protection for circuits. Instead, much like precision structural engineers, we build a circuit "defense system" on the PCB — one that neither interferes with signal transmission nor fails to instantly neutralize kilovolt-level electrical hazards.

For beginners in circuit protection, the small black components on a PCB — such as diodes and varistors — may seem insignificant. However, in real engineering environments, they serve as the only "armor" that protects electronic devices from external electrical disturbances.

Why Do Electronic Devices Need "Armor" Protection?

In the microscopic world of electronic components, electrostatic discharge (ESD) and surge are ubiquitous "invisible killers" — the friction of a simple turn in daily life can generate thousands of volts of static electricity, while a single lightning strike can induce enormous surge currents. Both pose fatal threats to electronic devices.

1.  External Core Threats: Electrostatic discharge (ESD) generated when a human body touches a device interface (must comply with IEC 61000-4-2) and lightning-induced surges on power lines (must comply with IEC 61000-4-5) can instantly puncture the oxide layer of downstream precision chips such as CPUs and LDOs, resulting in device damage.

2. Leiditech's core insight: Without the "armor" of protection devices, electronic equipment is not only highly susceptible to catastrophic damage, but also frequently suffers from stability issues such as packet loss and system crashes in complex electromagnetic environments, rendering it unable to function properly.

II. Core Terminology Explained: Capacitance and Clamping Voltage

Selection parameters are the most frequently asked questions to FAE engineers. For beginners in circuit protection, it is essential to understand the engineering trade-off logic behind the two "golden metrics" — capacitance and clamping voltage — as this forms the foundation of component selection.

1. Capacitance (C_J)

Capacitance directly determines the extent to which a protection device affects signal waveforms. In high-speed signal scenarios such as 40Gbps USB4 or 10G Ethernet (10GbE), a device's high parasitic capacitance can cause severe insertion loss, leading to eye diagram closure and ultimately resulting in communication failure. Therefore, protection devices for high-speed signal lines must achieve ultra-low capacitance at the 0.2pF level.

2. Clamping Voltage (V_C)

V_C is the core metric for evaluating the protection efficiency of a device. It refers to the actual voltage that can be effectively controlled across the device terminals when an electrical disturbance occurs. If V_C exceeds the breakdown voltage tolerance of the downstream chip, the precision chip behind it will be damaged or destroyed — even if the protection device itself remains intact.

Application Comparison of High-Capacitance vs. Low / Ultra-Low Capacitance Devices

III. The Core Dividing Line in Circuit Protection: Signal Protection vs. Power Protection

In circuit protection design, it is necessary to select appropriate protection devices based on the distinct requirements of the two different "battlefields": signal protection and power protection. The design logic and selection criteria for these two differ fundamentally:

1. 1. Success metrics differ: Signal protection prioritizes ultra-low capacitance (CJ) to ensure "transparency" in signal transmission without additional interference; power protection, on the other hand, pursues high peak pulse current capability (IPP) to achieve efficient surge current discharge.

2. 2. Circuit layout differs: Signal protection devices are typically connected in parallel between the signal line and ground, requiring extremely short traces to minimize signal loss. Power protection, however, serves as a robust surge discharge path and sometimes needs to be combined with inductors and PPTCs to form a "multi-stage coordinated" protection structure.

3. Failure consequences differ: When a signal protection device fails, it typically results in functional issues such as data errors or system crashes. In contrast, failure of a power protection device often leads to severe faults such as hardware burnout or complete equipment damage.

IV. Practical Protection Cases: Device Selection and Layout Guidelines for Different Scenarios

Case 1: Multi-Stage Protection for USB Interfaces

The USB interface is the primary channel for electrostatic discharge intrusion into electronic devices. For USB interfaces with different data rates, the selection logic for protection devices varies significantly and must be precisely matched:

1. USB 2.0 Industrial-Grade Protection: Civilian solutions often use the SR05, but for harsh industrial electromagnetic environments, the SR05W is recommended. It offers improved contact discharge protection, upgraded from 20kV to 30kV, making it capable of handling extreme interference scenarios.

2. USB 3.0 / Type-C Protection: For high-speed signals above 5Gbps, the ULC3304P10LV in DFN2510 package with feed-through routing is recommended. Differential pairs can be routed directly underneath the pins without the need for vias or stubs, perfectly maintaining 90Ω differential impedance and avoiding signal reflections.

3. USB 3.0 / Type-C Protection: For high-speed signals above 5Gbps, the ULC3304P10LV in DFN2510 package with feed-through routing is recommended. Differential pairs can be routed directly underneath the pins without the need for vias or stubs, perfectly maintaining 90Ω differential impedance and avoiding signal reflections.

USB Interface Layout Guideline: The ESD protection device must be placed as close as possible to the connector interface end, following the "discharge as close as possible" principle. This ensures that ESD is eliminated locally before it enters the PCB core area, preventing induced noise from coupling into internal traces.

Case 2: Precision Protection for SIM Cards and Buttons

SIM card protection is a typical space-constrained scenario. Its multiple pins (I/O, Clock, Reset, etc.) require simultaneous protection. The core design approach is "integration, small size, and high standards":

1. Integrated protection selection: Use the USRV05-4 (SOT-26 package) or the ULC0504P (DFN1616-6 package). A single device can provide full coverage protection for 4 to 5 pins, significantly saving PCB space.

2. Performance verification standards: The protection device must meet IEC 61000-4-2 Level 4 standards (8kV contact / 15kV air discharge). At the same time, the device capacitance must be controlled to avoid excessive capacitance that would slow signal edges and affect normal device operation.

Case 3: High Surge Protection at the Power Port

For the 24V DC power port, the protection focus shifts from ESD to high-energy surges. Traditional protection solutions have obvious shortcomings. Leiditech has introduced an optimized single-device solution:

1. Drawbacks of the traditional solution: Traditional DC surge protection uses a four-stage structure consisting of GDT (gas discharge tube) + MOV (metal oxide varistor) + inductor + TVS. Although it achieves 4kV surge protection, it is bulky and the inductor decoupling design is complex.

2. Leiditech optimized solution: Select a single LM1K24CA (SMB package). The core advantages are as follows:

3. 

o Low clamping voltage: The traditional solution has a clamping voltage of approximately 40V. The LM1K24CA can control the clamping voltage at 35V. This 5V safety margin effectively protects downstream LDO and DC-DC chips from breakdown.

o High surge protection: A single device can handle IEC 61000-4-5 surge testing at the 2kV level.

Expert recommendation for power port selection: The core metric for selecting power protection devices is the peak pulse current (IPP). If the IPP margin is insufficient, the device will quickly experience thermal breakdown when subjected to a surge, eventually resulting in a permanent short circuit and loss of protection capability

V. Pitfall Avoidance Guide: A Four-Step Method for Beginners in Protection Device Selection

To help engineers avoid common pitfalls in component selection, the following universal selection checklist has been compiled. By following these four steps, precise selection of protection devices can be achieved:

1. 1Confirm the working voltage (VRWM): This is the device's "stand-off voltage." At this voltage, the device must remain "transparent" without conducting or causing interference. When selecting a device, VRWM must be greater than the maximum operating voltage of the circuit (for example, choose a 5V device for a 5V rail — do not choose a 3.3V device, otherwise the device will falsely trigger and conduct).

2. Match package with available space: Select the device based on the actual PCB space. For high-speed lines, the DFN2510 feed-through package is the first choice. For power lines, the SMC or high-power SMB package is preferred.

3. Align with test standards: Select the device according to the test level required for the product. Determine the ESD protection level based on the IEC 61000-4-2 (ESD) standard, and determine the device's IPP power rating based on the IEC 61000-4-5 (Surge) standard.

4. Verify the clamping voltage (VC): Ensure that the clamping voltage (VC) of the protection device is lower than the damage voltage of the downstream chip, thereby providing effective protection.

Closing remarks

The theoretical knowledge of circuit protection is only the foundation of design; actual testing is the core truth for verifying protection effectiveness. Leiditech has its own built EMC laboratory. We sincerely invite all engineers to bring your product prototype boards for testing, observe the VC clamping curves on site, and verify whether your circuit's "armor" is robust enough to safeguard the stable operation of your product.